When analyzing the memory subsystem architecture of high-performance GPUs versus enterprise CPUs, which statement accurately characterizes their primary design differences regarding memory bandwidth and bus architecture?
Select an answer to reveal the explanation.
Short Explanation and Infographic
Here's the deal: CPUs and GPUs are built for completely different tasks. Think of a CPU like a high-speed sports car. It's designed to carry a small load (sequential tasks) from point A to point B incredibly fast with very low latency. A GPU, on the other hand, is like a massive multi-lane highway carrying thousands of delivery trucks at the same time (parallel workloads). To keep all those GPU cores fed with data, they need a massive memory pipeline. That's why GPUs use ultra-wide memory buses (like HBM or GDDR with widths of 384-bit, 512-bit, or even 2048-bit!) that deliver terabytes per second of bandwidth. CPUs typically have much narrower memory buses (like 64-bit or 128-bit per channel) which focus on super low latency rather than massive throughput. So don't let anyone tell you GPUs have inferior bandwidth—it's actually the exact opposite!
Full explanation below image
Full Explanation
The fundamental architectural divergence between CPUs and GPUs lies in their design optimization: latency optimization vs. throughput optimization. CPU memory systems are optimized for low latency. CPUs execute serial tasks where execution speed depends on how fast a single thread can fetch data from cache or RAM. Consequently, they utilize sophisticated cache hierarchies and narrow memory interfaces (typically 64-bit to 128-bit per channel). GPU memory systems are designed for high throughput to sustain thousands of arithmetic cores operating in parallel. To feed these cores, GPUs require massive memory bandwidth, which they achieve using extremely wide memory interfaces. For instance, GPUs utilizing High Bandwidth Memory (HBM) can feature memory interfaces wider than 2048 bits, delivering bandwidth in excess of 1-2 TB/s, compared to typical enterprise CPU bandwidth of 200-300 GB/s. Therefore, Choice B is correct. Choices A, C, and D represent incorrect descriptions of memory bus design and bandwidth metrics.