A utilities control DC observes GPUs idle despite queued training work. Telemetry shows the host PCIe root complex and NIC are saturated. What compute connectivity conclusion is most accurate?

Attributing the idle time to limited NVLink peer bandwidth between GPUs and expanding NVSwitch capacity to drain queued work faster misses the root cause; PCIe and NIC saturation can starve GPUs of data, making them idle despite running jobs. That conclusion works because compute connectivity evaluation looks beyond SM busy time—if PCIe and NICs are the ceiling, GPUs starve for data, collectives, or checkpoints regardless of how many jobs are queued. Concluding that streaming multiprocessor occupancy counters show the primary limit and tuning CUDA block sizing to refill the idle cycles overlooks that idle GPU SM often signals saturated host I/O; telemetry must span the entire datapath. Attributing the queued backlog to insufficient accelerator nodes and expanding the training cluster to refill idle GPU cycles faster fails as "remediation": it adds demand behind a saturated feed path instead of fixing the utilities AI feed path. Exam caveat: saturation can also stem from misconfigured NUMA/NIC affinity or a single overloaded storage mount; connectivity diagnosis should include topology and storage, not only buying faster NICs blindly. Operational check: correlate GPU idle fractions with PCIe and NIC counters during a queued training window, identify the saturated hop, and retest after widening that path (NIC, PCIe topology, or storage offload) before adding more GPUs.