A river buoy carries a purpose-built AI chip (an ASIC or system-on-chip) that does in-memory, multi-core inference, while the model itself was fitted in a cloud hall. How should the tester place that hardware?
Select an answer to reveal the explanation.
Short Explanation
A purpose-built ASIC or SoC on the river buoy is edge-oriented inference hardware, typically paired with cloud-side training. The buoy chip did not fit the model. Specialized AI chips can run inference at the edge; a general-purpose CPU is not the only hardware the syllabus names.
Full Explanation
Specialized ASIC / SoC hardware is typically used for edge inference, with training still elsewhere. Reversing training and inference, denying edge inference, or claiming only a CPU is named misses that comparison.